1. Field of the Invention
The present invention relates to a system for adjusting a sampling timing of a delay locked loop (DLL) circuit, a method therefor and a transmitter-receiver used therefor. In particular, the present invention relates to, in a data transmission system that uses the DLL circuit to achieve data synchronization between a transmitter side and a receiver side, a system for adjusting the sampling timing of the DLL circuit.
2. Description of the Prior Art
In recent data transmission between a transmitter and a receiver, a DLL circuit is used on the receiver side to achieve data synchronization while sampling received data (see Japanese Patent Laid-Open No. 7-84946). In this case, as the data transfer rate increases, the sampling timing of the DLL circuit may be shifted because of a temperature or voltage change, if data sequences having no data transition in the data pattern occur in succession.
Thus, for example, an 8B10B coding system may be used to suppress a shift of sampling timing of the DLL circuit. According to the 8B10B coding system, a data transition is caused intentionally. For example, if an original 8-bit data is data involving no data transition, such as data “00000000”, the data is converted into 10-bit data, such as “1001110100”. This advantageously prevents a shift of the sampling timing and an adverse effect of a signal pattern on a transmitted waveform, that is, the so-called inter-symbol interference (ISI).